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| MC14007UB Dual Complementary Pair Plus Inverter The MC14007UB multipurpose device consists of three N-Channel and three P-Channel enhancement mode devices packaged to provide access to each device. These versatile parts are useful in inverter circuits, pulse-shapers, linear amplifiers, high input impedance amplifiers, threshold detectors, transmission gating, and functional gating. Features http://onsemi.com MARKING DIAGRAMS 14 PDIP-14 P SUFFIX CASE 646 1 14 SOIC-14 D SUFFIX CASE 751A 1 14 Unit V V mA mW C C C A WL, L YY, Y WW, W G SOEIAJ-14 F SUFFIX CASE 965 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Indicator MC14007UB ALYWG 14007UG AWLYWW MC14007UBCP AWLYYWWG * Diode Protection on All Inputs * Supply Voltage Range = 3.0 Vdc to 18 Vdc * Capable of Driving Two Low-power TTL Loads or One Low-power * * * Schottky TTL Load Over the Rated Temperature Range Pin-for-Pin Replacement for CD4007A or CD4007UB This device has 2 outputs without ESD Protection. Antistatic precautions must be taken. Pb-Free Packages are Available MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 1) Ambient Temperature Range Storage Temperature Range Lead Temperature (8 second Soldering) Value -0.5 to +18.0 -0.5 to VDD +0.5 10 500 -55 to +125 -65 to +150 260 PIN ASSIGNMENT D-PB S-PB GATEB S-NB D-NB GATEA VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD D-PA OUTC S-PC GATEC S-NC D-NA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/C from 65C 5o 125C. D = DRAIN S = SOURCE ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. (c) Semiconductor Components Industries, LLC, 2006 October, 2006 - Rev. 8 1 Publication Order Number: MC14007UB/D MC14007UB A B 12 1 C INPUT VDD 14 3 5 2 4 C 11 INPUT 1 0 OUTPUT CONDITION A = C, B = OPEN A = B, C = OPEN Substrates of P-Channel devices internally connected to VDD; substrates of N-Channel devices internally connected to VSS. INPUT 13 6 8 10 9 B A 7 VSS Figure 1. Typical Application: 2-Input Analog Multiplexer 14 13 2 1 11 6 12 7 8 3 4 5 10 9 VDD = PIN 14 VSS = PIN 7 Figure 2. Schematic http://onsemi.com 2 I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII II III I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III III II III I I III I I I I I I I I III III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III IIIIIIII I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I III III III III I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I I I I I I III II III II II II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III IIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III I IIIII IIII IIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III I IIIII I IIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III I II IIIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III II II II I I III III IIII IIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I I I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III IIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIII IIII IIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II III III II III I II III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I I I I I III II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Symbol VOH VOL IOH VIH IDD IOL Cin VIL Iin IT Total Supply Current (Notes 3 and 4) (Dynamic plus Quiescent, Per Gate) (CL = 50 pF) Quiescent Current (Per Package) Input Capacitance (Vin = 0) Input Current Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Input Voltage (VO = 4.5 Vdc) (VO = 9.0 Vdc) (VO = 13.5 Vdc) Output Voltage Vin = VDD or 0 (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) (VO = 0.5 Vdc) (VO = 1.0 Vdc) (VO = 1.5 Vdc) Vin = 0 or VDD Characteristic "1" Level "0" Level "0" Level "1" Level Source Sink VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 - 2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 3. The formulas given are for the typical characteristics only at 25C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.003. http://onsemi.com MC14007UB -3.0 -0.64 -1.6 -4.2 4.95 9.95 14.95 0.64 1.6 4.2 4.0 8.0 12.5 Min - - - - - - - - - - - -55C 3 0.25 0.5 1.0 0.1 0.05 0.05 0.05 Max 1.0 2.0 2.5 - - - - - - - - - - - - - - -2.4 -0.51 -1.3 -3.4 4.95 9.95 14.95 IT = (0.7 mA/kHz) f + IDD/6 IT = (1.4 mA/kHz) f + IDD/6 IT = (2.2 mA/kHz) f + IDD/6 0.51 1.3 3.4 4.0 8.0 12.5 Min - - - - - - - - - - - 0.00001 Typ (Note 2) 0.0005 0.0010 0.0015 25C -5.0 -1.0 -2.5 -10 2.75 5.50 8.25 2.25 4.50 6.75 5.0 1.0 2.5 10 5.0 10 15 0 0 0 7.5 1.0 2.0 2.5 - - - - - - - - - - - - - 0.25 0.5 1.0 0.1 0.05 0.05 0.05 Max -1.7 -0.36 -0.9 -2.4 4.95 9.95 14.95 0.36 0.9 2.4 4.0 8.0 12.5 Min - - - - - - - - - - - 125C 1.0 0.05 0.05 0.05 Max 7.5 15 30 1.0 2.0 2.5 - - - - - - - - - - - - - - mAdc mAdc mAdc mAdc mAdc Unit Vdc Vdc Vdc Vdc pF MC14007UB IOH , DRAIN CURRENT (mAdc) IOL , DRAIN CURRENT (mAdc) I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII II I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII II II I I I IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I I IIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII II I IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25C) Symbol tTLH Characteristic VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min - - - - - - - - - - - - Typ (Note 6) 90 45 35 75 40 30 60 30 25 60 30 25 Max 180 90 70 150 80 60 125 75 55 125 75 55 Unit ns Output Rise Time tTLH = (1.2 ns/pF) CL + 30 ns tTLH = (0.5 ns/pF) CL + 20 ns tTLH = (0.4 ns/pF) CL + 15 ns Output Fall Time tTHL = (1.2 ns/pF) CL + 15 ns tTHL = (0.5 ns/pF) CL + 15 ns tTHL = (0.4 ns/pF) CL + 10 ns tTHL ns tPLH Turn-Off Delay Time tPLH = (1.5 ns/pF) CL + 35 ns tPLH = (0.2 ns/pF) CL + 20 ns tPLH = (0.15 ns/pF) CL + 17.5 ns Turn-On Delay Time tPHL = (1.0 ns/pF) CL + 10 ns tPHL = (0.3 ns/pF) CL + 15 ns tPHL = (0.2 ns/pF) CL + 15 ns ns tPHL ns 5. The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter. 6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. VDD = -VGS 14 IOH 7 VSS VDS = VOH - VDD 7 14 IOL VSS VDS = VOL VDD = VGS All unused inputs connected to ground. All unused inputs connected to ground. 0 -4.0 VGS = -5.0 Vdc -8.0 a TA = -55C b TA = +25C c TA = +125C c b a c b -10 Vdc c a a -15 Vdc b 20 16 a 12 b c a TA = -55C b TA = +25C c TA = +125C a c -0 0 0 2.0 b 5.0 Vdc a b c 10 Vdc VGS = 15 Vdc -12 8.0 -16 -20 -10 4.0 -8.0 -6.0 -4.0 VDS, DRAIN VOLTAGE (Vdc) -2.0 4.0 6.0 VDS, DRAIN VOLTAGE (Vdc) 8.0 10 Figure 3. Typical Output Source Characteristics Figure 4. Typical Output Sink Characteristics These typical curves are not guarantees, but are design aids. Caution: The maximum current rating is 10 mA per pin. http://onsemi.com 4 MC14007UB VDD 500 mF Vin 7 0.01 mF CERAMIC 14 Vout VSS CL Vout 20 ns Vin 90% 50% 10% tPHL 90% 50% 10% tTHL tTLH tPLH 20 ns VDD VSS VOH VOL ID PULSE GENERATOR Figure 5. Switching Time and Power Dissipation Test Circuit and Waveforms APPLICATIONS The MC14007UB dual pair plus inverter, which has access to all its elements offers a number of unique circuit applications. Figures 1, 6, and 7 are a few examples of the device flexibility. +V DD 2 DISABLE 3 1 11 13 11 2 VDD 14 OUT = A+B*C INPUT 10 12 OUTPUT B 10 12 8 1 OUTPUT 9 8 DISABLE 6 7 C 3 4 INPUT 1 0 X X = Don't Care DISABLE 0 0 1 OUTPUT 0 1 OPEN 6 9 5 7 A Substrates of P-Channel devices internally connected to VDD; Substrates of N-Channel devices internally connected to VSS. Figure 6. 3-State Buffer Figure 7. AOI Functions Using Tree Logic http://onsemi.com 5 MC14007UB ORDERING INFORMATION Device MC14007UBCP MC14007UBCPG MC14007UBD MC14007UBDG MC14007UBDR2 MC14007UBDR2G MC14007UBFEL MC14007UBFELG Package PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) 2000 / Tape & Reel 2500 / Tape & Reel 55 Units / Rail 25 Units / Rail Shipping For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 MC14007UB PACKAGE DIMENSIONS PDIP-14 CASE 646-06 ISSUE P 14 8 B 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10 _ 0.38 1.01 A F N -T- SEATING PLANE L C H G D 14 PL K M J M DIM A B C D F G H J K L M N 0.13 (0.005) http://onsemi.com 7 MC14007UB PACKAGE DIMENSIONS SOIC-14 CASE 751A-03 ISSUE H -A- 14 8 -B- P 7 PL 0.25 (0.010) M B M 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. G C -T- SEATING PLANE R X 45 _ F D 14 PL 0.25 (0.010) K M M S J TB A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 SOLDERING FOOTPRINT* 7X 7.04 1 0.58 14X 14X 1.52 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 MC14007UB PACKAGE DIMENSIONS SOEIAJ-14 CASE 965-01 ISSUE A 14 8 LE Q1 E HE M_ L DETAIL P 1 7 Z D e A VIEW P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056 c b 0.13 (0.005) M A1 0.10 (0.004) ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 9 MC14007UB/D |
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